(a) Field of the Invention
The invention relates to a delay adjustor, and particularly to a delay adjustor having high propagation delay time resolution.
(b) Description of the Related Art
Inside an integrated circuit, signal could be influenced by the parasitic capacitor of metal line, driving current, supply voltage and other factors and thereby generating the propagation delay time when the signal is transmitting. Such propagation delay time should be properly considered in some circuit applications. In general, the propagation delay time is given by:
                    Td        =                              C            I                    ×                      (                          1              2                        )                    ×          Vdd                                    (        1        )            
where Td is the propagation delay time, C is the parasitic capacitor, I is the driving current, and Vdd is the supply voltage. As an integrated circuit is influenced by process, voltage and temperature variation, the propagation delay time becomes unpredictable and may cause the integrated circuit to operate abnormally. Therefore, under certain circumstances, the propagation delay time needs to be well compensated. In the related prior arts, it is common to use the capacitor-paralleling method to adjust propagation delay time. In current processes, this approach can achieve about 10 ps adjustable resolution for propagation delay time. However, in some high-speed circuits or some special circuit applications, higher adjustable resolution is needed in order to improve the overall circuit characteristics.